As the CMOS image size and speed continue to increase, the column sample and hold array is becoming larger and time to read out a column S/H circuit is shorter. A decoder circuit is needed to address each individual S/H circuit within such S/H array to the output. The input address codes are sent to the decoder inputs through long buses which are usually the size of a row of pixels. Due to the large resistance and capacitance of the wires, these decoder addresses are sent the decoder with larger and larger delays as the column S/H circuit array is being read out one by one in the direction away from the decoder address drivers. These delays reduce the effective read-out time and cause noise at the output of the column S/H array. An additional delay which reduces as the column sample and hold array is read out is added to the decoder address buses to compensate the delay due to the bus parasitic resistance and capacitance.
Consequently, a need exists for a CMOS image sensor which corrects for the non-uniform delays at the column decoder output caused by the long address bus.